1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices and, more specifically, to the fabrication of double-sided capacitors and contacts using a sacrificial structure.
2. State of the Art
Capacitors are used in a wide variety of semiconductor circuits, such as in dynamic random access memory (“DRAM”) circuits. While the invention herein is discussed in relation to DRAM circuits, the applicability of the invention is not limited to DRAM circuits and may be used in any other type of memory circuits, such as static random access memory (“SRAM”) circuits or any other circuits in which capacitors are used.
DRAM circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell, usually consisting of a single metal-oxide semiconductor field effect transistor (“MOSFET”) and a single capacitor, is an addressable location that can store one bit (binary digit) of data. The DRAM cell stores a bit of data on the capacitor as an electrical charge. Manufacturing of the DRAM cell typically includes fabricating a transistor, a capacitor, and three contacts: one contact each to a bit line, a word line, and a reference voltage. DRAM manufacturing is a highly competitive business and there is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is also necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three-dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors that are stacked, or placed, over an access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than-4 four Megabits use stacked capacitors.
A widely used type of stacked capacitor is known as a container capacitor. Container capacitors are typically in the shape of an upstanding tube or cylinder having an oval or circular cross section. FIG. 1 illustrates a top view of a portion of a DRAM circuit from which the upper layers have been removed to reveal container capacitors 12 arranged around a bit line contact 14. Six container capacitors 12 are shown in FIG. 1, each of which is labeled with separate reference designations A to F. In FIG. 1, the bit line contact 14 is shared by DRAM cells corresponding to container capacitors A and B. The wall of each cylinder consists of two layers or plates of conductive material, such as doped polycrystalline silicon (referred to herein as “polysilicon” or “poly”) separated by a dielectric layer. One of the plates is a bottom electrode, while the second of the plates is a top electrode. The bottom end of the cylinder is closed, with the bottom electrode of the cylinder in contact with either a drain of the access transistor or a plug, which itself is in contact with the drain. The other end of the cylinder is open. Later in the fabrication process, the open end of the cylinder is filled with an insulative material. The sidewall and closed end of the cylinder form a container, which leads to the name “container capacitor.” Although the invention will be further discussed in connection with stacked container capacitors, it is understood that the invention is not limited thereto. For example, use of the invention in trench capacitors is also possible.
In addition to being conductive, the bottom and top electrodes in the DRAM cell capacitor protect the dielectric layer from interaction with interlayer dielectrics (e.g., borophosphosilicate glass (“BPSG”)) and from the harsh thermal processing encountered in subsequent processing. For instance, tantalum pentoxide (“Ta2O5”) is commonly used in the dielectric layer for high density DRAMs, such as 64-Mbit and 256-Mbit DRAMs, because chemical vapor deposition (“CVD”) of Ta2O5 provides a high dielectric constant (about 20-25) and good step coverage. However, when rapid thermally processed nitride (“RTN”) is formed over a layer of hemispherical grain polysilicon (“HSG”) to serve as an HSG barrier layer to prevent oxidation of HSG during subsequent Ta2O5 deposition, there is a capacitance loss due to the RTN layer on the capacitor electrode. The effective dielectric constant for an RTN/Ta2O5 stack capacitor is about 10-12.
Several approaches have been attempted to increase the capacitance in the container capacitor, such as by increasing the length of the capacitor and by increasing the surface area of the electrodes. For instance, the surface area of the electrodes has been increased by using HSG in the electrodes or by forming a double-sided capacitor. In the double-sided capacitor, the bottom electrode is typically surrounded on two sides by the top electrode, as described in U.S. Pat. No. 6,451,661 to DeBoer et al. Double-sided capacitors are typically formed by depositing the bottom electrode in an opening formed in a semiconductor wafer. The material of the bottom electrode is etched back or removed from a surface of the semiconductor wafer by chemical mechanical planarization (“CMP”). After etching a field oxide from the semiconductor wafer, the double-sided capacitor is formed on the semiconductor wafer surface. One problem with forming the double-sided capacitor is that the bottom electrode protrudes from the semiconductor wafer by about 1.5 μm to about 2 μm. The protruding bottom electrode is easily broken and causes problems with toppling. An additional problem is that the length of the top and bottom electrodes is limited due to problems with toppling. While it is possible to increase the electrode length by increasing the etch depth of the opening in which the electrodes are to be deposited, in practice, this causes a narrowing of the opening and, therefore, electrodes having the desired length are hard to achieve. Furthermore, a significant step height exists between the resulting capacitor and surrounding circuitry. The step height is difficult to reduce without depositing a thin layer of oxide and planarizing the layer. However, this adds an additional CMP step to the processing, which adds additional steps and complexity to the fabrication of the double-sided capacitor.
While double-sided capacitors are advantageous in that they provide additional capacitance, forming the double-sided capacitors is a complex process and requires additional processing steps. As memory cell density continues to increase, a double-sided capacitor having an increased effective capacitance per cell is needed. Furthermore, a double-sided capacitor that is formed using less complex processing techniques and fewer processing steps is needed.